Recruitment Detail
DFT Engineer
Build scan architecture, ATPG, and memory test infrastructure that keeps test cost down and coverage high.
DFT & Test Bangalore / Hybrid Full-time 3-8 years
Opportunity Overview
What this role covers
Build scan architecture, ATPG, and memory test infrastructure that keeps test cost down and coverage high.
Responsibilities
- Define scan and compression architecture
- Run ATPG and close test coverage
- Integrate MBIST / LBIST and JTAG
- Support tester bring-up and silicon debug
Requirements
Scan insertion and ATPG experience
Knowledge of JTAG / IEEE 1149.1
Fault models and coverage closure
Tessent, DFTMAX or equivalent tools
Preferred skills
Scan
ATPG
MBIST
JTAG
Fault Coverage
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