RTL Design Engineer
Own micro-architecture and synthesizable RTL for IP and subsystem blocks, through lint, CDC, and synthesis readiness.
Grow alongside engineers who care about clean silicon, real ownership, and cutting-edge technology.
Real ownership, strong mentorship, and exposure to cutting-edge silicon from day one.
Own micro-architecture and synthesizable RTL for IP and subsystem blocks, through lint, CDC, and synthesis readiness.
Build scan architecture, ATPG, and memory test infrastructure that keeps test cost down and coverage high.
Craft matched, reliability-aware custom layout for analog and mixed-signal blocks through physical signoff.
Drive multi-corner multi-mode timing closure and signoff for advanced-node blocks and full-chip.
A workplace that values engineers, celebrates wins, and keeps the energy high across every program.
Comprehensive medical cover for you and your family.
Hybrid and flexible schedules that respect focus time.
Sponsored courses, tool licences, and certification support.
Reward structures tied to delivery and ownership.
Generous leave policy for rest and life balance.
Clear growth tracks from engineer to technical lead.
Structured internships with real project exposure and mentoring.
Entry-level roles with a strong onboarding and training path.
Rotational programs across design, verification, and PD.
Regular hiring drives at engineering campuses.
Engineers and freshers across ASIC/SoC design, verification, physical design, DFT, FPGA, validation, and embedded systems.
Advanced-node ASIC/SoC programs using SystemVerilog/UVM, industry-standard EDA tools, and embedded platforms.
A short screening, a technical interview, and an HR discussion — usually completed within one to two weeks.
Yes — we support flexible and hybrid working depending on the role and program.
We are flexible on joining timelines and will align with your availability wherever possible.