Recruitment Detail
RTL Design Engineer
Own micro-architecture and synthesizable RTL for IP and subsystem blocks, through lint, CDC, and synthesis readiness.
Semiconductor Design Bangalore / Hyderabad Full-time 2-6 years
Opportunity Overview
What this role covers
Own micro-architecture and synthesizable RTL for IP and subsystem blocks, through lint, CDC, and synthesis readiness.
Responsibilities
- Translate specifications into micro-architecture
- Write and review synthesizable SystemVerilog RTL
- Close lint, CDC, and synthesis constraints
- Support integration and debug with DV teams
Requirements
Strong digital design fundamentals
SystemVerilog / Verilog RTL experience
Exposure to synthesis and timing concepts
Scripting in Python or Tcl
Preferred skills
SystemVerilog
RTL Design
Lint
CDC
Synthesis
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